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<p></p> <p><b>New page</b></p><div>'''Standard Parasitic Exchange Format''' ('''SPEF''') is an [[IEEE]] standard for representing parasitic data of wires in a chip in [[ASCII]] format. [[Electrical resistance|Resistance]], [[capacitance]] and [[inductance]] of wires in a chip are known as parasitic data. SPEF is used for [[delay calculation]] and ensuring [[signal integrity]] of a chip which eventually determines its speed of operation.<br /> <br /> SPEF is most popular specification for parasitic exchange between different tools of [[Electronic design automation|EDA]] domain during any phase of design.<br /> <br /> The specification for SPEF is a part of standard '''1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System'''.<br /> <br /> The brief syntax of the SPEF file is as shown :- <br /> <br /> .SUBCKT<br /> *I(InstancePinName InstanceName PinName PinType PinCap X Y)<br /> <br /> *P(PinName PinType PinCap X Y)<br /> <br /> *NET NetName NetCap<br /> <br /> *S(SubNodeName X Y)<br /> <br /> *GROUND_NET NetName</div>

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