Standard Parasitic Exchange Format

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Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Resistance, capacitance and inductance of wires in a chip are known as parasitic data. SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation.

SPEF is most popular specification for parasitic exchange between different tools of EDA domain during any phase of design.

The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.

The brief syntax of the SPEF file is as shown :-

.SUBCKT

  • I(InstancePinName InstanceName PinName PinType PinCap X Y)
  • P(PinName PinType PinCap X Y)
  • NET NetName NetCap
  • S(SubNodeName X Y)
  • GROUND_NET NetName